Time-to-Digital converters (TDCs) convert time intervals into a digital representation. There is a practical limit on the frequency of a master clock that can be used to measure time intervals. TDCs are primarily concerned with measuring time intervals between clock pulses of a master clock so as to offer a resolution better than would determined by the period of the master clock alone. TDCs have a number of applications, for example, in the field of particle physics, but an important application is the all-digital phase-locked loop (ADPLL), where they are used as phase detectors. Increasing demands in this field, in particular for wireless applications, such as mobile phones, Bluetooth, wireless LAN etc., call for TDCs with time resolutions in the order of picoseconds (ps). This is smaller than the clock period of the highest frequency practical clocks, so some method of interpolation must be employed to subdivide a clock period into smaller time intervals.
ADPLL designs should cover the frequency range from sub-100 MHz to 20 GHz (or even broader), which requires a wide phase detection range of tens of ns. It means that the TDC phase detection range needs to cover (not less than) the period of the lowest frequency of the DCO. Therefore, a fine TDC time resolution combined with a wide phase detection range is the most important performance specifications in most wireless applications. The other way to digitally express the phase detection range of a TDC is by how many output bits it produces. For instance, a 10 bit TDC with 2 ps resolution is able to detect 2 ns of the phase detection range, while a 14 bit TDC can cover more than 32 ns. In the case of a fixed number of digital bits, the phase detection range gets narrower with the finer TDC time resolution, which means that a TDC design must trade-off time resolution for phase detection range, or vice versa. Parameters such as area, power consumption and reliability are also important for assessing the TDC's overall performance.
One prior art technique is to use a digital delay line consisting of a chain of inverter delay elements as shown in FIG. 1a. The delay elements divide one clock interval into a series of small time intervals. Delayed versions of a leading signal are sampled in parallel along the delay line. The DCO input represents the leading signal, which serves as a start signal and the REF input serves as the triggering signal. The TDC measures the time interval between the leading signal and the triggering signal.
Coincidence with the triggering signal is detected by a chain of D flip-flops. The D flip-flops capture the value of the D-input at a definite portion of the clock cycle (e.g. the rising edge of the clock or falling edge). An odd number of D flip-flops are triggered by the falling edge; an even number of D flip-flops are triggered by the rising edge. That captured value becomes the Q output.
As shown in FIG. 1b, when the triggering signal transitions from low to high the Q outputs of the flip-flops are latched to the input value. The leading signal appears inverted at the output of the first inverter and the D-input of the first flip-flop after a first delay. Similarly, the leading signal appears uninverted at the output of the second inverter and the D-input of the first flip-flop after a second delay. As soon as the triggering signal goes high, the Q output of the flip-flops will follow their respective D-inputs, giving a sequence of ones and zeros at the input to the decoder which represents the time difference between the low to high transition of the leading to the triggering signal as shown in FIG. 1b. This results in a thermometer code because all the delay stages that have been passed by the leading signal, prior to the transition of the reference signal, give a high value output, when corrected for the number of inversions, whereas the delay stages that have not been passed by the leading signal will have a low value output when corrected for the number of inversions. The position of the high-low transition indicates how far the leading signal could propagate during the time interval spanned by the leading and triggering signals.
An alternative arrangement, shown in FIG. 2, is to employ a ring oscillator consisting of k delay stages. The ring oscillator has a better phase detection range because leading signal can run multiple times through the ring before triggering signal arrives, therefore making it in theory to support infinite detection range; requires a small chip area because of the limited number of delay elements; and has a lower power consumption than the digital delay line because of the fewer components, but still suffers from poor phase noise performance because the resolution is limited to the delay of one delay element, typically 16 ps.
Both the digital delay line and ring oscillator TDCs have relatively coarse time resolution. An improvement can be realized by modifying the digital delay line to employ the Vernier principle. In a conventional Vernier instrument, a Vernier scale is set along side a main scale, where the Vernier scale spacing is a fraction of the main scale spacing. Typically ten graduations of the Vernier scale correspond to nine graduations of the main scale. This means that if the starting graduation on the Vernier scale is aligned with a graduation on the main scale, the second Vernier graduation will be offset by 1/10th of the main scale, the third by 2/10 ths and so on until the tenth, which will align with the 9th graduation on the main scale. Alternatively, if the first Vernier graduation is aligned somewhere between graduations on the main scale, the first coincidence between the Vernier scale graduation and the main scale graduation will indicate the fraction of the graduations on the main scale where the first Vernier graduation is located.
A similar principle can be employed in the time domain by using two delay lines with slightly different delays. In this case the clock edges constitute the graduations. If the Vernier delay line with a slightly different delay is started when a triggering event occurs between two main clock edges, the next time a coincidence occurs between a Vernier clock edge and a main clock edge will give a measure of the fractional distance of the event between the main clock edges that is dependent on the difference in delays of the two delay lines.
Such a TDC is shown in FIG. 3, where the time resolution Tres is given by the expression Tres=ΔT=τ2−τ1, where τ2 represents the per inverter delay for the leading signal and τ1 represents the per inverter delay for the trigger signal. While offering a fine resolution, this arrangement has a narrow phase detection range, requires a large chip area and has high power consumption.
The Vernier delay-line TDC can be improved by looping the two delay lines to create a fast and slow ring as shown in FIG. 4. This strategy improves the phase detection range, and moderately reduces the required chip area and power consumption. The chip area and power consumption however remain a significant factor. One example of such a TDC is described in U.S. Pat. No. 8,138,958, the contents of which are herein incorporated by reference.